In advanced very-large-scale integrated circuits, the power lines of circuits are separated to avoid noise coupling and to reduce ground bouncing for high-performance circuit operation. However, according to previous investigation integrated circuits with separated power pins and separated power lines [1]-[4] interface circuits are more sensitive to ESD (electrostatic-discharge) damage, even if suitable, ESD protection circuits are placed around the input and output pads of the circuits.
[1] N. Maene, J. Vandenbroeck, and L. Bempt, "On chip electrostatic discharge protections for inputs, outputs, and supplies of CMOS circuits," Proc. of EOS/ESD Symp., 1992, pp. 228-233. PA1 [2] M.-D. Ker and T.-L. Yu, "ESD protection to overcome internal gate-oxide damage on digital-analog interface of mixed-mode CMOS IC's," Journal of Microelectronics and Reliability, vol. 36, no. 11/12, 1996, pp. 1727-1730. PA1 [3] M.-D. Ker, C.-Y. Wu, T. Cheng, M. Wu, T.-L Yu, and A. Wang, "Whole-chip ESD protection for CMOS VLSI/ULSI with multiple power pins," Proc. of 1994 IEEE International Integrated Reliability Workshop, USA, Oct. 16-19, 1994, pp. 124-128. PA1 [4] M.-D. Ker, C.-Y. Wu, H.-H. Chang, and T.-S. Wu, "Whole-chip ESD protection scheme for CMOS mixed-mode IC's in deep-submicron CMOS technology," Proc. of IEEE Custom Integrated Circuits Conference, USA, 1997, pp. 31-34. PA1 [5] EOS/ESD Standard for ESD Sensitivity Testing, EOS/ESD Association, Inc., NY., 1993. PA1 [6] S. Dabral, R. Aslett, and T. Maloney, "Designing on-chip power supply coupling diodes for ESD protection and noise immunity," Proc. of EOS/ESD Symp., 1993, pp. 239-249. PA1 [7] T. Maloney and S. Dabral, "Novel clamp circuits for IC power supply protection," Proc. of EOS/ESD Symp., 1995, pp. 1-12. PA1 [8] H. Nguyen and J. Walker, "Electrostatic discharge protection system for mixed voltage application specific integrated circuit design," U.S. Pat. No. 5,616,943, April, 1997. PA1 [9] J. Kuo, "ESD protection scheme," U.S. Pat. No. 5,196,981, March, 1993. PA1 [10] J. Leach, "Method of forming an electrostatic discharge protection circuit," U.S. Pat. No. 5,290,724, March, 1994. PA1 [11] W. Miller, "Electrostatic discharge protection for CMOS integrated circuits," U.S. Pat. No. 5,301,084, April, 1994. PA1 [12] W. Reczek and H. Terletzki, "Integrated semiconductor circuit with ESD protection," U.S. Pat. No. 5,426,323, June, 1995. PA1 [13] T. Maloney, "Electrostatic discharge protection circuits using biased and terminated PNP transistor chains," U.S. Pat. No. 5,530,612, June, 1996. PA1 [14] S. Voldman, "Power sequence independent electrostatic discharge protection circuits," U.S. Pat. No. 5,610,791, March, 1997. PA1 [15] S. Voldman, "Voltage regulator bypass circuit," U.S. Pat. No. 5,625,280, April, 1997. PA1 [16] E. Worley, et al., "Sub-micron chip ESD protection schemes which avoid avalanching junction," Proc. Of EOS/ESD Symp., 1995, pp. 13-20.
ESD stress may occur across any two pins of an integrated circuit (IC). The ESD current may enter into the IC through an input or output pin, and then flow out the IC from another input or output pin. Thus, the pin-to-pin ESD stress has been referred to as an ESD-testing condition. In the pin-to-pin ESD-testing condition, which is found in ESD testing standard [5], a positive or negative ESD voltage is applied to the input or output pin and simultaneously the other input or output pin are grounded. However, all of the VDD and Vss pins are floating. This pin-to-pin ESD testing condition frequently inflicts unexpected ESD damage on internal circuits.
To avert such unexpected ESD damage on the internal circuits, some approaches try to add a series of diode string between the separated power lines of IC, [6]-[8]. Several U.S. patents and investigations [9]-[16] have reported on a similar design by using diodes', MOS'S, BJT's, or field-oxide devices (or called as Thick-oxide device) to connect the separated power lines of a CMOS IC.
FIG. 1 depicts the typical design of ESD protection circuits according to prior art. An IC comprises of circuit I and circuit II. Protected by ESD protection devices, circuit I and circuit II are internal circuits of integrated circuits.
Power line VDD, and power line V.sub.SS1 are coupled with circuit I and is indicated as the power supplies of circuit I.
According to prior art illustrated in FIG. 1, power line V.sub.DD1 is coupled with power line V.sub.DD2 through a diode string 600 and power line V.sub.SS1 is coupled with the power line V.sub.SS2 through a diode string 500. The number of diodes in the diode strings depends on the voltage level or the noise level between the separated power lines. The additional diode strings between the separated power lines are designed to conduct the ESD current between the separated power lines to avert the ESD damage incurred at the internal circuits when the IC is under the ESD stress condition. However, when the IC is under normal operating conditions with the normal supplies, the diode string is designed to block the voltage or noise between the separated power lines. If the IC has much more separated power lines in the chip, bi-directional diode strings must be added between every two adjacent power lines. FIG. 2 shows a typical example using the bi-directional diode strings to connect the separated power lines of the CMOS IC with four circuitry.
FIG. 2 also contains four circuitry with four separated power pairs in the drawing. Circuit I is supplied by V.sub.DD1 and V.sub.SS1. Circuit II is supplied by V.sub.DD2 and V.sub.SS2. Circuit III is supplied by V.sub.DD3 and V.sub.SS3. Circuit IV is supplied by V.sub.DD4 and V.sub.SS4. Bi-directional diode strings 500 are therefore added between V.sub.DD1 and V.sub.DD2, between V.sub.DD2 and V.sub.DD3, and between V.sub.DD3 and V.sub.DD4. Bi-directional diode strings 500 are also added between V.sub.SS1 and V.sub.SS2, between V.sub.SS2 and V.sub.SS3, and between V.sub.SS3 and V.sub.SS4. Such bi-directional diode strings 500 provide the ESD-current conducting path between the separated power lines when the IC is under ESD-stress conditions. An example of the pin-to-pin ESD-stress condition can be found in FIG. 2, in which a positive ESD voltage is attached to input pad 100 of circuit I. However, input pad 100 of circuit IV is relatively grounded. During this pin-to-pin ESD stress, the positive ESD voltage/current is initially conducted into the V.sub.DD1 (or V.sub.SS1) through diode Dp1 (Dn1) in input ESD protection circuit on input pad 100 of circuit I. Such ESD voltage/current on the V.sub.DD1 (V.sub.SS1) is conducted into the V.sub.DD2 (V.sub.SS2) through the diode string between the V.sub.DD1 and V.sub.DD2 (V.sub.SS1 and V.sub.SS2). According to the dashed lines in FIG. 2, I.sub.ESD is then conducted into the V.sub.DD4 (or V.sub.SS4) through the diode strings 500 between the separated power lines of the IC. Finally, the ESD voltage/current is discharged from grounded input pad 100 of circuit IV to the ground through the diodes Dp4 or Dn4 of the input ESD protection circuit on the input pad 100. According to FIG. 2, the ESD current must be discharged through at least three diode strings, before the ESD current emits from grounded input pad 100 of circuit IV. Consider a situation in which the IC has a large number of separated power lines to supply a large number of different circuitry. The larger the number of diode strings in the ESD-current discharging path implies a longer discharging delay to bypass the ESD current away from the integrated circuits through these diode strings. Therefore, the integrated circuit may still occure ESD damage. Therefore, the ESD protection design concept of FIG. 1 is no longer appropriate for the VLSI circuit, which has a large number of separated power lines.